The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 27, 2017
Filed:
Jan. 11, 2013
Applicant:
Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;
Inventor:
Kazuo Tomita, Kawasaki, JP;
Assignee:
RENESAS ELECTRONICS CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/58 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/585 (2013.01); H01L 23/528 (2013.01); H01L 23/5283 (2013.01); H01L 23/53295 (2013.01); H01L 23/564 (2013.01); H01L 23/3114 (2013.01); H01L 23/3157 (2013.01); H01L 23/5226 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/05567 (2013.01); H01L 2224/13022 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/13091 (2013.01);
Abstract
A semiconductor device is a semiconductor device in which one chip region is formed through divided exposure. An interlayer insulating film has a via and an interconnection trench in an element formation region and has a guard ring hole in a guard ring region. An interconnection conductive layer is formed in the via and the interconnection trench. A guard ring conductive layer is formed in the guard ring hole. A minimum dimension of a width of the guard ring conductive layer is greater than a minimum dimension of a width of the interconnection conductive layer in the via.