The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2017

Filed:

May. 04, 2015
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Uei-Ming Jow, San Diego, CA (US);

Young Kyu Song, San Diego, CA (US);

Jong-Hoon Lee, San Diego, CA (US);

Xiaonan Zhang, San Diego, CA (US);

Mario Francisco Velez, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/336 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 23/50 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49827 (2013.01); H01L 21/486 (2013.01); H01L 21/4857 (2013.01); H01L 23/49805 (2013.01); H01L 23/49811 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 23/50 (2013.01); H01L 24/17 (2013.01); H01L 2224/16055 (2013.01); H01L 2224/16057 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/16237 (2013.01); H01L 2924/15311 (2013.01);
Abstract

An integrated circuit device that includes a package substrate and a die coupled to the package substrate. The package substrate includes at least one dielectric layer, a first stack of first interconnects in the at least one dielectric layer, and a second interconnect formed on at least one side portion of the at least one dielectric layer. The first stack of first interconnects is configured to provide a first electrical path for a non-ground reference signal, where the first stack of first interconnects is located along at least one side of the package substrate. The second interconnect is configured to provide a second electrical path for a ground reference signal.


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