The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2017

Filed:

Mar. 08, 2016
Applicant:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Inventors:

Mari Matsumoto, Kanagawa, JP;

Shinichi Yasuda, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); G11C 5/02 (2006.01); G11C 5/06 (2006.01); G11C 17/16 (2006.01); H03K 19/177 (2006.01);
U.S. Cl.
CPC ...
G11C 17/16 (2013.01); H03K 19/1776 (2013.01); G11C 5/02 (2013.01); G11C 5/06 (2013.01); G11C 13/0002 (2013.01); G11C 13/003 (2013.01); G11C 13/0004 (2013.01); G11C 2213/77 (2013.01);
Abstract

A semiconductor integrated circuit according to an embodiment includes a plurality of first wiring lines electrically connected to a plurality of input wiring lines; a plurality of second wiring lines electrically connected to a plurality of output wiring lines, the second wiring lines crossing the first wiring lines; and a plurality of cell arrays each of which includes memory elements disposed at intersection regions of a part of the first wiring lines and a part of the second wiring lines, each of the memory elements including a first terminal and a second terminal, the first terminal being electrically connected to one of the first wiring lines, the second terminal being electrically connected to one of the second wiring lines, and each of the second wiring lines being electrically connected to at most one of the cell arrays.


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