The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2017

Filed:

Aug. 23, 2016
Applicants:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Stmicroelectronics Design & Application S.r.o., Praha, CZ;

Inventors:

Marco Pasotti, Travacò Siccomario, IT;

Fabio De Santis, Milan, IT;

Roberto Bregoli, Offlaga, IT;

Dario Livornesi, Paderno Dugnano, IT;

Sandor Petenyi, Milovice Nad Labem, CZ;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); G11C 16/30 (2006.01); H01L 27/11521 (2017.01); G11C 16/28 (2006.01); G11C 16/04 (2006.01); G11C 5/14 (2006.01);
U.S. Cl.
CPC ...
G11C 16/30 (2013.01); G11C 5/147 (2013.01); G11C 16/0408 (2013.01); G11C 16/10 (2013.01); G11C 16/28 (2013.01); H01L 27/11521 (2013.01);
Abstract

A device for generating a reference voltage includes a first non-volatile memory cell provided with a control-gate transistor and a reading transistor. The control-gate transistor includes a gate terminal, a body, a first conduction terminal and a second conduction terminal. The first conduction terminal and the second conduction terminal are connected together to form a control-gate terminal. The reading transistor includes a gate terminal that is connected to the gate terminal of the control-gate transistor to form a floating-gate terminal, a body, a third conduction terminal and a fourth conduction terminal. The device also includes a second, equivalent, memory cell. The source terminal of the first non-volatile memory cell and the source terminal of the second equivalent memory cell are connected together.


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