The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2017

Filed:

Apr. 09, 2015
Applicant:

Sharp Kabushiki Kaisha, Sakai, Osaka, JP;

Inventors:

Yutaka Takamaru, Sakai, JP;

Seiji Kaneko, Sakai, JP;

Takao Saitoh, Sakai, JP;

Yohsuke Kanzaki, Sakai, JP;

Keisuke Ide, Sakai, JP;

Hiroshi Matsukizono, Sakai, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1362 (2006.01); G02F 1/1333 (2006.01); G02F 1/1368 (2006.01); G02F 1/1343 (2006.01);
U.S. Cl.
CPC ...
G02F 1/136227 (2013.01); G02F 1/1362 (2013.01); G02F 1/1368 (2013.01); G02F 1/13439 (2013.01); G02F 1/133345 (2013.01); G02F 1/134363 (2013.01);
Abstract

A TFT substrate (A) of a liquid crystal display panel includes: an organic interlayer insulating layer () covering a TFT; a first transparent electrically-conductive layer () provided in the first region of a surface of the organic interlayer insulating layer (); and an inorganic dielectric layer () covering the first transparent electrically-conductive layer () and provided in a second region of the surface of the organic interlayer insulating layer () which is different from the first region, the inorganic dielectric layer () containing SiN, wherein an arithmetic mean roughness Ra of the first region and the second region of the surface of the organic interlayer insulating layer () is not less than 3.45 nm and not more than 5.20 nm.


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