The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 27, 2017
Filed:
Apr. 20, 2015
Oracle International Corporation, Redwood City, CA (US);
Sebastian Turullols, Los Altos, CA (US);
Vijay Srinivasan, Menlo Park, CA (US);
Changku Hwang, Morgan Hill, CA (US);
Oracle International Corporation, Redwood City, CA (US);
Abstract
Implementations of the present disclosure involve a system and/or method for measuring on-die voltage levels of an integrated circuit through a digital sampling circuit. In particular, the system and/or method utilize a delay line based analog-to-digital sampling circuit that produces a voltage reading over time, such as at every high frequency clock cycle. In one embodiment, the digital sampling circuit may include a clock jitter monitor circuit configured with a constant supply voltage. This clock jitter monitor is configured to measure the clock jitter that is experienced by the digital voltage monitor circuit and, when compared to measured voltage captured by the circuit, may be used to calibrate or otherwise correct the readings provided by the digital voltage monitor circuit.