The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 2017

Filed:

Sep. 17, 2014
Applicant:

Htc Corporation, Taoyuan County, TW;

Inventors:

Ta-Shun Chu, Hsinchu, TW;

Ta-Chun Pu, Taoyuan County, TW;

Chun-Yih Wu, Taoyuan County, TW;

Assignee:

HTC Corporation, Taoyuan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01S 13/02 (2006.01); H03L 7/08 (2006.01); H03L 7/23 (2006.01); G01S 7/03 (2006.01);
U.S. Cl.
CPC ...
H03L 7/08 (2013.01); G01S 7/032 (2013.01); H03L 7/23 (2013.01);
Abstract

A high resolution timing device is provided. The high resolution timing device includes a first and a second clock delay circuits. The first clock delay circuit receives an input reference clock signal to generate a first multiple frequency output clock signal, divide the first multiple frequency output clock signal to generate a first original frequency output clock signal and perform a clock-delaying process thereon according to the first multiple frequency output clock signal to generate first clock-delayed signals. The second clock delay circuit receives one of the first clock-delayed signals to generate a second multiple frequency output clock signal, divide the second multiple frequency output clock signal to generate a second original frequency output clock signal and perform the clock-delaying process thereon according to the second multiple frequency output clock signal to generate second clock-delayed signals.


Find Patent Forward Citations

Loading…