The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9685241 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 20, 2017

Filed:

Mar. 18, 2015
Applicant:

Fujitsu Limited, Kawasaki-shi, Kanagawa, JP;

Inventor:

Koji Kuroda, Fuji, JP;

Assignee:

FUJITSU LIMITED, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G06F 11/00 (2006.01); G11C 29/12 (2006.01); G11C 8/16 (2006.01);
U.S. Cl.
CPC ...
G11C 29/1201 (2013.01); G11C 8/16 (2013.01);
Abstract

A test circuit includes a control circuit that tests a memory having a plurality of data holding circuits holding data, a plurality of write ports, and a plurality of read ports, a write port selection circuit that selects any one of the plurality of write ports based on the write port identification information identifying any one of the plurality of write ports; and a read port selection circuit that selects any one of the plurality of read ports based on the read port identification information identifying any one of the plurality of read ports, wherein the control circuit sets the write port identification information and sets the read port identification information and carries out a test on the memory via the selected write port and the selected read port.


Find Patent Forward Citations

Kuroda, Koji. (2017). Memory test circuit and method for controlling memory test circuit (U.S. Patent No. 9685241). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9685241

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