The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 20, 2017
Filed:
Aug. 24, 2016
Applicant:
SK Hynix Inc., Gyeonggi-do, KR;
Inventors:
Se Hun Kang, Gyeonggi-do, KR;
Deok Sin Kil, Gyeonggi-do, KR;
Assignee:
SK Hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/22 (2006.01); H01L 27/1159 (2017.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 29/06 (2006.01); H01L 29/51 (2006.01); H01L 43/00 (2006.01); H01L 43/08 (2006.01);
U.S. Cl.
CPC ...
G11C 11/223 (2013.01); G11C 11/22 (2013.01); G11C 11/221 (2013.01); H01L 27/1159 (2013.01); H01L 29/0649 (2013.01); H01L 29/0684 (2013.01); H01L 29/0847 (2013.01); H01L 29/513 (2013.01); H01L 29/516 (2013.01); H01L 29/517 (2013.01); H01L 29/7827 (2013.01); H01L 29/78391 (2014.09); H01L 43/00 (2013.01); H01L 43/08 (2013.01);
Abstract
A semiconductor memory device may include a pillar, a gate and at least one ferroelectric layer. The pillar may include a source, a drain and a channel region. The drain may be arranged over the source. The channel region may be arranged between the source and the drain. The gate may be formed on an outer surface of the pillar. The ferroelectric layer may be interposed between the pillar and the gate.