The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 2017

Filed:

Jul. 23, 2013
Applicants:

Myung-hoon Choi, Suwon-si, KR;

Jae-yong Jeong, Yongin-si, KR;

Ki-tae Park, Seongnam-si, KR;

Inventors:

Myung-Hoon Choi, Suwon-si, KR;

Jae-Yong Jeong, Yongin-si, KR;

Ki-Tae Park, Seongnam-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 16/26 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/34 (2006.01); G11C 29/44 (2006.01); G11C 29/02 (2006.01); G11C 16/00 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1057 (2013.01); G11C 11/5642 (2013.01); G11C 16/0483 (2013.01); G11C 16/26 (2013.01); G11C 16/3431 (2013.01); G11C 29/021 (2013.01); G11C 29/028 (2013.01); G11C 29/44 (2013.01); G11C 16/00 (2013.01);
Abstract

A memory device includes a memory cell array having a plurality of memory cells, and a page buffer unit including a plurality of page buffers configured to store a plurality of pieces of data sequentially read from some of the plurality of memory cells at different read voltage levels, respectively, and to perform a logic operation on the plurality of pieces of data, respectively. The memory device further includes a counting unit configured to count the number of memory cells that exist in each of a plurality of sections defined by the different read voltage levels, based on results of the logic operation.


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