The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 2017

Filed:

Nov. 06, 2014
Applicant:

Silicon Motion, Inc., Jhubei, Hsinchu County, TW;

Inventors:

Chien-Cheng Lin, Yilan, TW;

Chia-Chi Liang, Taichung, TW;

Chang-Chieh Huang, Zhubei, TW;

Jie-Hao Lee, Kaohsiung, TW;

Assignee:

SILICON MOTION, INC., Jhubei, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/14 (2006.01); G06F 3/06 (2006.01); G06F 11/10 (2006.01); G06F 12/12 (2016.01); G11C 29/52 (2006.01); G11C 29/04 (2006.01); G06F 12/02 (2006.01); G06F 12/121 (2016.01);
U.S. Cl.
CPC ...
G06F 11/1469 (2013.01); G06F 3/0604 (2013.01); G06F 3/0652 (2013.01); G06F 3/0679 (2013.01); G06F 11/1072 (2013.01); G06F 12/0246 (2013.01); G06F 12/121 (2013.01); G11C 29/52 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/69 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7202 (2013.01); G06F 2212/7203 (2013.01); G06F 2212/7209 (2013.01); G11C 2029/0411 (2013.01); Y02B 60/1225 (2013.01);
Abstract

A data storage device and a flash memory control method with high erasing efficiency are disclosed. A microcontroller is configured to maintain a plurality of logical-to-physical address mapping tables and a link table on a flash memory to record mapping information between a host and the flash memory. The link table indicates positions of the plurality of logical-to-physical address mapping tables, and each entry in the link table corresponds to one logical-to-physical address mapping table. When erasing user data of logical addresses corresponding to N logical-to-physical address mapping tables, the microcontroller is configured to invalidate N entries corresponding to the N logical-to-physical address mapping tables in the link table, where N is an integer.


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