The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 2017

Filed:

Mar. 28, 2014
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Diyanesh B. Chinnakkonda Vidyapoornachary, Bangalore, IN;

Edgar R. Cordero, Round Rock, TX (US);

Anand Haridass, Bangalore, IN;

Arun Joseph, Bangalore, IN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 3/06 (2006.01); G06F 13/28 (2006.01); G06F 13/42 (2006.01); G06F 12/0893 (2016.01);
U.S. Cl.
CPC ...
G06F 3/0625 (2013.01); G06F 1/3275 (2013.01); G06F 1/3293 (2013.01); G06F 3/0647 (2013.01); G06F 3/0656 (2013.01); G06F 3/0658 (2013.01); G06F 3/0673 (2013.01); G06F 12/0893 (2013.01); G06F 13/28 (2013.01); G06F 13/4247 (2013.01); G06F 2212/1028 (2013.01); G06F 2212/151 (2013.01); Y02B 60/1228 (2013.01); Y02B 60/1235 (2013.01);
Abstract

According to embodiments of the disclosure, methods, systems and computer program products for memory power management and data consolidation are disclosed. The method may include selecting a first real memory portion and a second real memory portion from a plurality of real memory portions coupled to a memory controller in a computer system by a memory bus. The first real memory portion may be connected to a first buffer and the second real memory portion may be connected to a second buffer. The first and second real memory portions may be selected by the memory controller. The method may include migrating data from the first real memory portion to the second real memory portion on a migration bus through the first and second buffers. The method may also include placing the first real memory portion into a reduced power mode.


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