The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2017

Filed:

Apr. 13, 2015
Applicant:

Renesas Electronics Corporation, Kawasaki-shi, JP;

Inventor:

Hiroyuki Takahashi, Kawasaki, JP;

Assignee:

RENESAS ELECTRONICS CORPORATION, Kawasaki-Shi, Kanagawa, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 5/02 (2006.01); G11C 11/4099 (2006.01); G11C 7/02 (2006.01); G11C 11/4097 (2006.01); G11C 11/4074 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4099 (2013.01); G11C 7/02 (2013.01); G11C 11/4097 (2013.01); G11C 11/4074 (2013.01);
Abstract

Provided is a semiconductor device including: a memory cell array including a plurality of memory cells disposed in a matrix; and a peripheral circuit adjacent to the memory cell array. Each of the memory cells includes: a capacitive element including a lower electrode having a cylinder shape extending in a direction perpendicular to a principal surface of a substrate; and a switch transistor provided between the capacitive element and a bit line, turning on/off of the switch transistor being controlled based on a potential of a word line. The peripheral circuit includes a signal line that is adjacent to the lower electrode in a horizontal direction parallel to the principal surface and is supplied with a fixed potential, or a pair of signal lines respectively supplied with complementary potentials.


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