The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2017

Filed:

Jun. 14, 2016
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Yohei Yasuda, Yokohama, JP;

Hiromitsu Komai, Kamakura, JP;

Kensuke Yamamoto, Yokohama, JP;

Masaru Koyanagi, Tokyo, JP;

Yasuhiro Hirashima, Kawasaki, JP;

Assignee:

KABUSHIKI KAISHA TOSHIBA, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/04 (2006.01); G11C 7/06 (2006.01); H03F 3/16 (2006.01); G11C 7/22 (2006.01);
U.S. Cl.
CPC ...
G11C 7/06 (2013.01); G11C 7/22 (2013.01); H03F 3/16 (2013.01);
Abstract

According to one embodiment, an amplifier includes a first inverter which inverts and delays a first signal to generate a second signal. A second inverter inverts and delays a third signal to generate a fourth signal. A first transistor includes a gate electrode supplied with the second signal. A second transistor includes a gate electrode supplied with the fourth signal. An output terminal is coupled to one terminal of the second transistor and outputs a fifth signal. A third inverter inverts and delays the fifth signal to generate a sixth signal. A first discharge circuit discharges one terminal of the first transistor and the one terminal of the second transistor based on the first, sixth, or fourth signal, and includes one terminal coupled to the other terminal of each of the first and second transistors.


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