The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2017

Filed:

Nov. 03, 2015
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Pradip K. Jha, Cupertino, CA (US);

Ravi N. Kurlagunda, Fremont, CA (US);

David A. Knol, Los Gatos, CA (US);

Dinesh K. Monga, Santa Clara, CA (US);

Stephen P. Rozum, Loveland, CO (US);

Sudipto Chakraborty, Longmont, CO (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5045 (2013.01); G06F 17/5031 (2013.01); G06F 17/505 (2013.01); G06F 17/5022 (2013.01);
Abstract

Constraint handling for a circuit design may include determining, using a processor, instances of parameterizable modules of a circuit design associated with constraints based upon a predefined hardware description language attribute within the instances, extracting, using the processor, parameter values from the instances of the parameterizable modules, and generating, using the processor, static constraint files for the instances of the parameterizable modules using the extracted parameter values.


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