The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2017

Filed:

Jan. 16, 2015
Applicant:

Oracle International Corporation, Redwood City, CA (US);

Inventor:

John Fernando, Austin, TX (US);

Assignee:

Oracle International Corporation, Redwood Shores, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/0811 (2016.01); G11C 11/406 (2006.01); G06F 12/1009 (2016.01); G06F 12/123 (2016.01); G06F 12/084 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0811 (2013.01); G06F 12/1009 (2013.01); G06F 12/123 (2013.01); G11C 11/40615 (2013.01); G06F 12/084 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/65 (2013.01); G06F 2212/69 (2013.01);
Abstract

A method and apparatus for memory paging is disclosed. A system includes a plurality of processor cores each configured to initiate requests to a memory by providing a physical address without a virtual address. A first cache subsystem is shared by each of a first subset of the plurality of processor cores. Responsive to receiving a memory access request from a processor core of the first subset, the first cache subsystem determines if a physical address of the request is in a first paged region of memory with respect to the first subset. If the physical address is in the paged region, the cache subsystem is configured to access a set of page attributes for a page corresponding to the physical address from a page attribute table responsive that is shared by each of the first subset of the plurality of processor cores.


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