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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9678154 B1

PDFFull Text
Date of Patent:
Jun. 13, 2017

Filed:

Oct. 30, 2014

Circuit techniques for efficient scan hold path design

Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Animesh Datta, San Diego, CA (US);

Qi Ye, San Diego, CA (US);

Steven James Dillen, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:

Loza & Loza, LLP

Primary Examiner:

Christine Tu

Int. Cl.
CPC ...
G01R 31/28 (2006.01); G01R 31/317 (2006.01); G01R 31/3177 (2006.01); H03K 5/133 (2014.01); H03K 5/134 (2014.01); G11C 7/10 (2006.01); G11C 29/32 (2006.01); G01R 31/3185 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31725 (2013.01); G01R 31/3177 (2013.01); G01R 31/31727 (2013.01); G11C 7/1057 (2013.01); G11C 7/1066 (2013.01); G11C 29/32 (2013.01); H03K 5/133 (2013.01); H03K 5/134 (2014.07); G01R 31/318541 (2013.01); G11C 2029/3202 (2013.01);
Abstract

In one embodiment, a method for signal delay in a scan path comprises, in a scan mode, delaying a scan signal in the scan path by propagating the scan signal through a plurality of delay devices coupled in series, wherein a first one of the delay devices is powered by a first voltage, a second one of the delay devices is powered by a second voltage, and the second voltage is greater than the first voltage. The method also comprises, in a functional mode, disabling the delay devices.

Find Patent Forward Citations

Datta, Animesh. (2017). Circuit techniques for efficient scan hold path design (U.S. Patent No. 9678154). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9678154

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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