The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 13, 2017
Filed:
Apr. 07, 2014
Applicant:
Imec, Leuven, BE;
Inventors:
Assignee:
IMEC, Leuven, BE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/20 (2006.01); G01R 31/26 (2014.01); H01L 21/66 (2006.01); G01R 31/3185 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2644 (2013.01); G01R 31/2601 (2013.01); G01R 31/318505 (2013.01); H01L 22/32 (2013.01); H01L 25/065 (2013.01); G01R 31/26 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/15311 (2013.01);
Abstract
The present invention relates generally to testing of interconnects in a semiconductor die, and more particularly to testing of semiconductor chips that are three-dimensionally stacked via an interposer. In one aspect, a method for testing an interconnect in a semiconductor die comprises providing the semiconductor die, which includes a plurality of electrical contact elements formed at one or more surfaces of the semiconductor die, at least one interconnect-under-test disposed between a first electrical contact element and a second electrical contact element, and an electrical component electrically coupled between the interconnect-under-test and at least one third electrical contact element.