The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2017

Filed:

Apr. 12, 2016
Applicant:

Entropic Communications, Llc, Carlsbad, CA (US);

Inventors:

Branislav Petrovic, La Jolla, CA (US);

Carl Harry Alelyunas, Austin, TX (US);

Assignee:

ENTROPIC COMMUNICATIONS, LLC, Carlsbad, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 7/08 (2006.01); H04L 27/10 (2006.01); H04L 25/49 (2006.01); H03M 3/00 (2006.01); H04B 1/692 (2011.01); H04B 1/717 (2011.01); H03M 1/82 (2006.01); H04L 27/04 (2006.01); H04B 1/707 (2011.01); H04B 1/7163 (2011.01);
U.S. Cl.
CPC ...
H04L 27/103 (2013.01); H03M 1/822 (2013.01); H03M 3/506 (2013.01); H04B 1/692 (2013.01); H04B 1/7172 (2013.01); H04L 25/4902 (2013.01); H04L 27/04 (2013.01); H04B 1/707 (2013.01); H04B 1/71632 (2013.01); H04B 2201/71638 (2013.01);
Abstract

Methods and systems are provided for spreading spectral density of pulse streams during digital to analog conversion. An example spreading circuit may comprise an accumulator circuit, a bit generator circuit, a comparator circuit, and an inverter circuit. The accumulator circuit may be operable to receive a signal to be spread and generate an output based on the signal to be spread and at least one other input. The bit generator circuit may be operable to input into the accumulator circuit zero-sum sequences. The comparator circuit may be operable to provide a stream of pulses based on the output of the accumulator circuit. The inverter circuit may be operable to invert output of the comparator circuit, wherein output of the inverter circuit is input into the accumulator circuit.


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