The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2017

Filed:

Sep. 30, 2015
Applicant:

Mellanox Technologies Tlv Ltd., Ra'anana, IL;

Inventors:

Liron Mula, Ramat Gan, IL;

Ran Ravid, Tel Aviv, IL;

Oded Wertheim, Zichron Yaakov, IL;

Ran Sela, Givat Shmuel, IL;

Roy Kriss, Netanya, IL;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); H04L 1/00 (2006.01); H04L 29/08 (2006.01);
U.S. Cl.
CPC ...
H04L 1/0045 (2013.01); H04L 1/0041 (2013.01); H04L 69/323 (2013.01); H04L 69/324 (2013.01);
Abstract

Communication apparatus includes a PHY interface, which is configured to receive over a communication link and to decode a sequence of symbols arranged in a series of data blocks. The PHY interface includes an error correction circuit, which when actuated, corrects errors in decoded data symbols using FEC symbols in the data blocks. The decoded data include data packets containing respective error detection codes. A memory buffers the data blocks received by the PHY interface. A data link layer interface receives the data packets from the PHY interface, checks the data packets using respective error detection codes, and upon detecting an error in a given data packet, signals the PHY interface to read from the memory at least one buffered data block that contains the given data packet while actuating the error correction circuit to correct the error using the FEC symbols in the at least one buffered data block.


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