The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2017

Filed:

Aug. 07, 2014
Applicant:

Postech Academy-industry Foundation, Pohang-si, Gyeongsangbuk-do, KR;

Inventors:

Jae Yoon Sim, Pohang-si, KR;

Seung Hwan Hong, Seoul, KR;

Assignee:

POSTECH ACADEMY-INDUSTRY FOUNDATION, Pohang-si, Gyeongsangbuk-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/197 (2006.01); H03L 7/083 (2006.01); H03L 7/099 (2006.01); H03L 7/23 (2006.01); G04F 10/00 (2006.01); H03L 7/095 (2006.01); H03M 3/00 (2006.01);
U.S. Cl.
CPC ...
H03L 7/1974 (2013.01); G04F 10/005 (2013.01); H03L 7/083 (2013.01); H03L 7/095 (2013.01); H03L 7/0992 (2013.01); H03L 7/0995 (2013.01); H03L 7/1976 (2013.01); H03L 7/23 (2013.01); H03M 3/39 (2013.01); H03L 2207/50 (2013.01);
Abstract

The present invention relates to a technique capable of implementing a frequency synthesizer circuit separated into a frequency synthesizer circuit part and an injection locked PLL circuit part and sequentially performing a frequency synthesizer lock operation and an injection lock operation to implement fast frequency and phase locking. The present invention comprises: a frequency synthesizer configured to perform a frequency and phase lock operation according to fractional number information and a first reference cock signal supplied from outside and thereby output a reset signal and a second reference clock signal; and an injection locked PLL configured to start a frequency lock operation after being reset by the reset signal inputted when the frequency synthesizer is frequency-locked, receive the second reference clock signal as a reference clock, multiply the second reference clock signal by an integer multiple of target frequency, and output an output clock signal.


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