The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 06, 2017
Filed:
Apr. 28, 2015
Applicant:
Dsp Group Ltd.;
Inventor:
Assaf Ganor, Herzeliya, IL;
Assignee:
DSP GROUP LTD., Herzliya, IL;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H04L 5/00 (2006.01); H03K 19/0185 (2006.01); H03K 3/012 (2006.01); H03K 3/013 (2006.01); H03K 3/037 (2006.01); H03K 19/20 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 19/018507 (2013.01); H03K 3/012 (2013.01); H03K 3/013 (2013.01); H03K 3/037 (2013.01); H03K 5/00 (2013.01); H03K 19/20 (2013.01); H03K 2005/00013 (2013.01);
Abstract
A scheme is described that provides for a low latency, glitch free chip interface that does not require a clock. This invention handles input transitions that are skewed and also input transitions that are momentary. A change in an input state initiates a pulse that propagates through the system and samples the new input state after a delay. If there is a difference between the sampled input state and the present input state, then a new pulse is initiated in order to avoid any illegal transitions at the output.
Quick Actions:
Ganor, Assaf. (2017). Low latency glitch-free chip interface (U.S. Patent No. 9673820). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9673820
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile