Digital pulse width detection based duty cycle correction

Abstract

Systems and methods for generating periodic signals with reduced duty cycle variation are described. In some cases, a calibration procedure may be performed prior to a memory operation (e.g., prior to a read operation or a programming operation) in which a duty cycle correction circuit receives an input signal (e.g., an input clock signal), steps through various delay settings to determine a first delay setting corresponding with a signal high time for the input signal and a second delay setting corresponding with a signal low time for the input signal, generates a delayed version of the input signal corresponding with a mid-point delay setting between the first delay setting and the second delay setting, and generates a corrected signal using the delayed version of the input signal and the input signal.