The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2017

Filed:

Feb. 08, 2016
Applicant:

Mstar Semiconductor, Inc., Hsinchu Hsien, TW;

Inventors:

Meng-Tse Weng, Zhubei, TW;

Jiunn-Yih Lee, Zhubei, TW;

Assignee:

MStar Semiconductor, Inc., Hsinchu Hsien, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/04 (2006.01); H03K 5/13 (2014.01); H03K 21/02 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 5/13 (2013.01); H03K 21/026 (2013.01); H04L 7/04 (2013.01); H03K 2005/00052 (2013.01);
Abstract

An integrated circuit includes a data sampler and a digital logic circuit. The data sampler provides multiple signal samples at a speed twice a symbol rate according to a local clock signal and the inverted local clock signal. The signal samples include a first symbol sample, and a second symbol sample that occurs later than the first symbol sample. The signal samples further include an interpolated sample between the first and second symbol samples. The digital logic circuit compares the first symbol sample with the interpolated sample to generate pre phase correction data, and compares the second symbol sample with the interpolated sample to generate post phase correction data. The pre phase correction data is generated earlier than the post phase correction data. The local clock signal and the inverted local clock signal have substantially a phase difference of 180 degrees.


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