The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2017

Filed:

Sep. 22, 2015
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Lipeng Cao, La Jolla, CA (US);

Jeffrey Gemar, San Diego, CA (US);

Ramaprasath Vilangudipitchai, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/012 (2006.01); H03K 3/3562 (2006.01); H03K 3/037 (2006.01); H03K 3/356 (2006.01);
U.S. Cl.
CPC ...
H03K 3/012 (2013.01); H03K 3/0372 (2013.01); H03K 3/3562 (2013.01); H03K 3/356008 (2013.01);
Abstract

Data retention circuitry, such as at least one integrated circuit (IC), is disclosed herein for power multiplexing with flip-flops having a retention feature. In an example aspect, an IC includes a first power rail and a second power rail. The IC further includes a flip-flop and power multiplexing circuitry. The flip flop includes a master portion and a slave portion. The master portion is coupled to the first power rail for a regular operational mode and for a retention operational mode. The power multiplexing circuitry is configured to couple the slave portion to the first power rail for the regular operational mode and to the second power rail for the retention operational mode.


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