The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9673333 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 06, 2017

Filed:

Feb. 22, 2016
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Zheng Liu, Beijing, CN;

Xiaoyong Lu, Beijing, CN;

Xiaolong Li, Beijing, CN;

Yu-Cheng Chan, Beijing, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 27/02 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78621 (2013.01); H01L 27/02 (2013.01); H01L 27/124 (2013.01); H01L 27/127 (2013.01); H01L 27/1222 (2013.01); H01L 27/1255 (2013.01); H01L 27/1288 (2013.01); H01L 29/786 (2013.01); H01L 29/78645 (2013.01); H01L 29/78675 (2013.01); H01L 29/78696 (2013.01);
Abstract

A method for fabricating a Polysilicon Thin-Film Transistor is provided. The method includes forming a polysilicon active layer, forming a first gate insulation layer and a first gate electrode sequentially on the active layer, conducting a first ion implantation process on the active layer by using the first gate electrode as a mask to form two doped regions at ends of the active layer, forming a second gate insulation layer and a second gate electrode sequentially on the first gate insulation layer and the first gate electrode, and conducting a second ion implantation process on the active layer by using the second gate electrode as another mask to form two source/drain implantation regions at two outer sides of the doped regions of the active layer. Accordingly, impurity concentration of the two doped regions is smaller than that of the two source/drain implantation regions.


Find Patent Forward Citations

Liu, Zheng. (2017). P-si tft and method for fabricating the same, array substrate and method for fabricating the same, and display device (U.S. Patent No. 9673333). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9673333

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