The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2017

Filed:

Dec. 14, 2015
Applicants:

Hannstar Display (Nanjing) Corporation, Nanjing, CN;

Hannstar Display Corporation, Taipei, TW;

Inventors:

Chien-Hao Wu, Taipei, TW;

Yi-Ting Lee, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 23/544 (2006.01); H01L 29/66 (2006.01); H01L 27/12 (2006.01); H01L 21/441 (2006.01); H01L 29/24 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 23/544 (2013.01); H01L 21/441 (2013.01); H01L 27/1225 (2013.01); H01L 27/1262 (2013.01); H01L 29/24 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 2223/5442 (2013.01); H01L 2223/54426 (2013.01); H01L 2223/54486 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A method for manufacturing a semiconductor device is provided. The method comprises the steps of: providing a transparent substrate having a visible region and an invisible region; forming a gate and at least an alignment mark coplanarly on the transparent substrate, wherein the gate is located in the visible region and the alignment mark is located in the invisible region; forming a gate insulation layer to cover the gate and cover the alignment mark; forming an oxide semiconductor layer on the gate insulation layer above the gate; and forming an etching stop layer above the gate and the alignment mark.


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