The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 06, 2017
Filed:
May. 25, 2012
Applicants:
Shuichi Oka, Kanagawa, JP;
Shusaku Yanagawa, Kanagawa, JP;
Kiwamu Adachi, Kanagawa, JP;
Inventors:
Assignee:
SONY CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/16 (2006.01); H01G 4/005 (2006.01); H01G 4/33 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
H01G 4/005 (2013.01); H01G 4/33 (2013.01); H01L 21/4857 (2013.01); H01L 23/49805 (2013.01); H01L 23/49822 (2013.01); H05K 1/162 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15331 (2013.01); H01L 2924/3011 (2013.01); H01L 2924/30107 (2013.01); H05K 3/4652 (2013.01); Y10T 156/10 (2015.01);
Abstract
A multilayer wiring board includes: a functional area which includes a thin film capacitor having a dielectric layer between an upper electrode and a lower electrode; and a peripheral area other than the functional area, wherein a mooring portion in which the dielectric layer and a conductive layer are laminated is provided in at least a portion of the peripheral area, and a roughness of a surface of the conductive layer which contacts the dielectric layer is greater than a roughness of a surface of the upper electrode or the lower electrode which contacts the dielectric layer.