The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 06, 2017
Filed:
Mar. 10, 2016
Applicant:
Apple Inc., Cupertino, CA (US);
Inventors:
Arik Rizel, Hod Hasharon, IL;
Avraham Poza Meir, Rishon le-Zion, IL;
Yael Shur, Tel Aviv, IL;
Eyal Gurgi, Petah-Tikva, IL;
Barak Baum, Givatayim, IL;
Assignee:
Apple Inc., Cupertino, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 16/10 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); H01L 29/423 (2006.01); H01L 27/11568 (2017.01);
U.S. Cl.
CPC ...
G11C 16/24 (2013.01); G11C 11/5671 (2013.01); G11C 16/0466 (2013.01); G11C 16/0475 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); H01L 27/11568 (2013.01); H01L 29/42328 (2013.01);
Abstract
A device includes a memory and a read/write (R/W) unit. The memory includes multiple gates coupled to a common charge-trap layer. The R/W unit is configured to program and read the memory by creating and reading a set of electrically-charged regions in the common charge-trap layer, wherein at least a given region in the set is not uniquely associated with any single one of the gates.