The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2017

Filed:

Sep. 18, 2014
Applicant:

Bitdefender Ipr Management Ltd., Nicosia, CY;

Inventors:

Andrei V. Lutas, Satu Mare, RO;

Sandor Lukacs, Floresti, RO;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/00 (2013.01); G06F 21/55 (2013.01); G06F 21/56 (2013.01); G06F 21/53 (2013.01); G06F 9/455 (2006.01); H04L 29/06 (2006.01); G06F 12/08 (2016.01); G06F 12/1027 (2016.01); G06F 12/109 (2016.01); G06F 12/14 (2006.01);
U.S. Cl.
CPC ...
G06F 21/554 (2013.01); G06F 9/45558 (2013.01); G06F 12/08 (2013.01); G06F 12/109 (2013.01); G06F 12/1027 (2013.01); G06F 12/1475 (2013.01); G06F 21/53 (2013.01); G06F 21/56 (2013.01); H04L 63/145 (2013.01); G06F 2009/45587 (2013.01); G06F 2221/033 (2013.01);
Abstract

Described systems and methods enable a host system to efficiently perform computer security activities, when operating in a hardware virtualization configuration. A processor is configured to generate a VM suspend event (e.g., a VM exit or a virtualization exception) when a guest instruction executing within a guest VM performs a memory access violation. In some embodiments, the processor is further configured to delay generating the VM suspend event until the execution stage of the pipeline for the guest instruction is complete, and to save results of the execution stage to a specific location (e.g. a specific processor register readable by security software) before generating the event.


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