The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2017

Filed:

May. 01, 2014
Applicant:

Oracle International Corporation, Redwood Shores, CA (US);

Inventors:

Zoran Radovic, Alvsjo, SE;

Jared C. Smolens, Santa Clara, CA (US);

Robert T. Golla, Austin, TX (US);

Paul J. Jordan, Austin, TX (US);

Mark A. Luttrell, Cedar Park, TX (US);

Assignee:

Oracle International Corporation, Redwood Shores, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/30 (2006.01); G06F 11/08 (2006.01); G06F 9/30 (2006.01); G06F 9/38 (2006.01);
U.S. Cl.
CPC ...
G06F 17/30985 (2013.01); G06F 9/30043 (2013.01); G06F 9/3834 (2013.01); G06F 9/3855 (2013.01); G06F 9/3859 (2013.01); G06F 11/08 (2013.01); G06F 17/30309 (2013.01); G06F 17/30507 (2013.01); G06F 17/30864 (2013.01);
Abstract

Techniques for executing versioned memory access instructions. In one embodiment, a processor is configured to execute versioned store instructions of a first thread within a first mode of operation. In this embodiment, in the first mode of operation, the processor is configured to retire a versioned store instruction only after a version comparison has been performed for the versioned store instruction. In this embodiment the processor is configured to suppress retirement of instructions in the first thread that are younger than an oldest versioned store instruction until the oldest versioned store instruction has retired. In some embodiments, the processor is configured to execute versioned store instructions of a given thread within a second mode of operation, in which the processor is configured to retire outstanding versioned store instructions before a version comparison has been performed.


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