The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9672103 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 06, 2017

Filed:

Sep. 08, 2015
Applicant:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Inventors:

Yoshifumi Nishi, Kanagawa, JP;

Takao Marukame, Tokyo, JP;

Yuichiro Mitani, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/03 (2006.01); G06F 11/10 (2006.01); H03M 13/11 (2006.01); H03M 13/00 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1068 (2013.01); H03M 13/1125 (2013.01); H03M 13/6597 (2013.01);
Abstract

According to an embodiment, a decoding device includes a check node processor, and a converter. The probability acquirer is configured to acquire. The check node processor is configured to perform check node processing during in a decoding operation of encoded data. A probability value for each bit of the encoded data is treated as an initial variable node in the check node processing. The converter is configured to convert, into bit values, updated values of the probability values based on the check node processing. The check node processor includes a check node circuit having a topology corresponding to a two-state trellis diagram representing the check node processing. The check node circuit includes conducting wires each corresponding to an edge of the two-state trellis diagram and includes switch units which are arranged on the conducting wires and switching of which is controlled according to a predetermined probability.


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