The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2017

Filed:

Nov. 20, 2015
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Benjamin Andrew Keller, Oakland, CA (US);

Matthew Rudolph Fojtik, Raleigh, NC (US);

Brucek Kurdo Khailany, Austin, TX (US);

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G06F 5/06 (2006.01); G11C 7/22 (2006.01); G11C 8/16 (2006.01);
U.S. Cl.
CPC ...
G06F 5/06 (2013.01); G11C 7/222 (2013.01); G11C 8/16 (2013.01); G06F 2205/061 (2013.01); G11C 2207/2254 (2013.01); G11C 2207/2272 (2013.01);
Abstract

A system, method, and computer program product are provided for a pausible bisynchronous FIFO. Data is written synchronously with a first clock signal of a first clock domain to an entry of a dual-port memory array and an increment signal is generated in the first clock domain. The increment signal is determined to transition near an edge of a second dock signal, where the second clock signal is a pausible clock signal. A next edge of the second clock signal of the second clock domain is delayed and the increment signal to the second clock domain and is transmitted.


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