The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2017

Filed:

Aug. 13, 2014
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Steven Goss, Addison, TX (US);

Gregory Remy Philippe Conti, Saint Paul, FR;

Narendar M. Shankar, San Jose, CA (US);

Mehdi-Laurent Akkar, Paris, FR;

Aymeric Vial, Antibes, FR;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04L 9/32 (2006.01); G06F 12/14 (2006.01); G06F 21/57 (2013.01); G06F 21/79 (2013.01); H04L 29/06 (2006.01); H04L 12/06 (2006.01); G06F 12/08 (2016.01); H04L 9/08 (2006.01); G06F 9/455 (2006.01); G06F 9/46 (2006.01); G06F 12/02 (2006.01); H04W 12/06 (2009.01);
U.S. Cl.
CPC ...
H04L 9/3236 (2013.01); G06F 9/45558 (2013.01); G06F 9/461 (2013.01); G06F 12/0246 (2013.01); G06F 12/145 (2013.01); G06F 12/1408 (2013.01); G06F 12/1483 (2013.01); G06F 21/575 (2013.01); G06F 21/79 (2013.01); H04L 9/0897 (2013.01); H04L 63/18 (2013.01); H04L 63/20 (2013.01); H04W 12/06 (2013.01); G06F 12/08 (2013.01); G06F 2009/45583 (2013.01); G06F 2009/45587 (2013.01); G06F 2212/171 (2013.01); G06F 2212/402 (2013.01); G06F 2212/7201 (2013.01); Y02B 60/1225 (2013.01);
Abstract

A secure demand paging system includes a processor operable for executing instructions, an internal memory for a first page in a first virtual machine context, an external memory for a second page in a second virtual machine context, and a security circuit coupled to the processor and to the internal memory for maintaining the first page secure in the internal memory. The processor is operable to execute sets of instructions representing: a central controller, an abort handler coupled to supply to the central controller at least one signal representing a page fault by an instruction in the processor, a scavenger responsive to the central controller and operable to identify the first page as a page to free, a virtual machine context switcher responsive to the central controller to change from the first virtual machine context to the second virtual machine context; and a swapper manager operable to swap in the second page from the external memory with decryption and integrity check, to the internal memory in place of the first page.


Find Patent Forward Citations

Loading…