The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2017

Filed:

Mar. 30, 2016
Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventors:

Pei-Heng Hung, New Taipei, TW;

Manoj Kumar, Dhanbad, IN;

Hsiung-Shih Chang, Taichung, TW;

Chia-Hao Lee, New Taipei, TW;

Jun-Wei Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/735 (2006.01); H01L 29/73 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 21/8222 (2006.01); H01L 21/762 (2006.01); H01L 29/423 (2006.01); H01L 29/40 (2006.01); H01L 29/861 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7302 (2013.01); H01L 21/76264 (2013.01); H01L 21/8222 (2013.01); H01L 29/0649 (2013.01); H01L 29/402 (2013.01); H01L 29/41708 (2013.01); H01L 29/42304 (2013.01); H01L 29/6609 (2013.01); H01L 29/6625 (2013.01); H01L 29/66128 (2013.01); H01L 29/66136 (2013.01); H01L 29/735 (2013.01); H01L 29/861 (2013.01); H01L 29/8611 (2013.01);
Abstract

The invention provides a semiconductor device, including a buried oxide layer disposed on a substrate. A semiconductor layer is disposed on the buried oxide layer. A first well is disposed in the semiconductor layer. A second well and a third well are disposed to opposite sides of the first well and separated from the first well. An isolation feature covers the first well and the third well. A poly field plate is disposed on the isolation feature and over the semiconductor layer between the first well and the third well. A first anode doped region is disposed on the second well. A second anode doped region and a third anode doped region are disposed on the second well. The second anode doped region is positioned directly on the third anode doped region. A first cathode doped region is coupled to the third well.


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