The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2017

Filed:

Jul. 25, 2013
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventor:

Nam Kyun Park, Gyeonggi-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); H01L 27/24 (2006.01); H01L 45/00 (2006.01); H01L 27/22 (2006.01);
U.S. Cl.
CPC ...
H01L 27/249 (2013.01); H01L 27/228 (2013.01); H01L 27/2436 (2013.01); H01L 45/04 (2013.01); H01L 45/06 (2013.01); H01L 45/1226 (2013.01); H01L 45/14 (2013.01); H01L 45/141 (2013.01); H01L 45/147 (2013.01); H01L 45/1666 (2013.01); G11C 13/003 (2013.01); G11C 2213/71 (2013.01); G11C 2213/75 (2013.01);
Abstract

A variable resistance memory device and a driving method thereof are provided. The variable resistance memory device includes a base layer and a pillar-shaped gate electrode formed on the base layer and extending substantially perpendicular to a surface of the base layer. A current transfer layer is formed to surround the pillar-shaped gate electrode. A variable resistance layer formed in an outer portion of the current transfer layer. A blocking layer blocks a path of current flowing through the current transfer layer based on a voltage applied voltage to the pillar-shaped gate electrode, and diverts the current flowing through the current transfer layer to the variable resistance layer.


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