The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2017

Filed:

Jan. 15, 2015
Applicant:

Qualcomm Incorporated, San Deigo, CA (US);

Inventors:

Oscar Law, San Diego, CA (US);

Chunchen Liu, San Diego, CA (US);

Ju-Yi Lu, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 25/065 (2006.01); H03K 17/00 (2006.01); H03K 17/56 (2006.01); G11C 29/12 (2006.01); G11C 29/48 (2006.01); H01L 23/538 (2006.01); G01R 31/3185 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); G01R 31/318513 (2013.01); G11C 29/1201 (2013.01); G11C 29/48 (2013.01); H01L 23/5384 (2013.01); H01L 23/5385 (2013.01); H03K 17/002 (2013.01); H03K 17/56 (2013.01); H01L 22/32 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06572 (2013.01); H01L 2225/06596 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A three-dimensional integrated circuit (3D-IC) architecture incorporates multiple layers, each layer including at least one die and at least one switch to connect the dies on the different layers. In some aspects, a power distribution network (PDN) is routed from a first layer through the switches to supply power to at least one other layer, thereby reducing routing congestion on the layers. The switches can be placed around the periphery of an IC package to improve heat dissipation (e.g., by improving heat transfer from the center to the edge of the IC package). The switches can be used for routing test signals and/or other signals between layers, thereby improving test functionality and/or fault recovery.


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