The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2017

Filed:

Aug. 10, 2015
Applicants:

California Institute of Technology, Pasadena, CA (US);

Texas A&m University System, College Station, TX (US);

Inventors:

Anxiao Jiang, College Station, TX (US);

Eyal En Gad, Pasadena, CA (US);

Jehoshua Bruck, Pasadena, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 11/56 (2006.01); G06F 12/02 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G11C 16/0441 (2013.01); G06F 3/0619 (2013.01); G06F 3/0643 (2013.01); G06F 3/0679 (2013.01); G06F 12/0246 (2013.01); G11C 11/5621 (2013.01); G11C 11/5628 (2013.01); G11C 11/5635 (2013.01); G11C 16/0483 (2013.01); H03M 2201/52 (2013.01);
Abstract

Rank modulation has been recently proposed as a scheme for storing information in flash memories. Three improved aspects are disclosed. In one aspect the minimum push-up scheme, for storing data in flash memories is provided. It aims at minimizing the cost of changing the state of the memory. In another aspect, multi-cells, used for storing data in flash memories is provided. Each transistor is replaced with a multi-cell of m transistors connected in parallel. In yet another aspect, multi-permutations, are provided. The paradigm of representing information with permutations is generalized to the case where the number of cells in each level is a constant greater than one.


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