The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2017

Filed:

May. 30, 2014
Applicants:

Regents of the University of Minnesota, Minneapolis, MN (US);

Palkesh Jain, Bangalore, IN;

Gracieli Posser, Porto Alegre, BR;

Ricardo Reis, Porto Alegre, BR;

Inventors:

Sachin S. Sapatnekar, Minneapolis, MN (US);

Vivek Mishra, Minneapolis, MN (US);

Palkesh Jain, Bangalore, IN;

Gracieli Posser, Porto Alegre, BR;

Ricardo Reis, Porto Alegre, BR;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5081 (2013.01); G06F 17/5072 (2013.01); G06F 17/5077 (2013.01); G06F 2217/06 (2013.01); G06F 2217/08 (2013.01); G06F 2217/78 (2013.01); G06F 2217/82 (2013.01);
Abstract

A circuit design system includes a simulator that determines an average charging current provided by each current insertion point in a cell and an average charging current along a path in the cell between a reference pin position and a candidate pin position. A candidate pin placement tester updates the average charging current along the path by adding the average charging current of each insertion point to the average charging current along the path to produce an updated average charging current along the path and uses the updated average charging current along the path to determine a time to failure for the cell.


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