The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 30, 2017
Filed:
May. 22, 2013
Applicant:
Xockets, Inc., San Jose, CA (US);
Inventor:
Parin Bhadrik Dalal, Milpitas, CA (US);
Assignee:
Xockets, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/00 (2013.01); G06F 13/16 (2006.01); G06F 17/30 (2006.01); H04L 29/06 (2006.01); G06F 21/55 (2013.01); H04L 29/08 (2006.01); G06F 12/1018 (2016.01); G06F 12/1081 (2016.01); G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
G06F 13/16 (2013.01); G06F 13/1652 (2013.01); G06F 9/5066 (2013.01); G06F 12/1018 (2013.01); G06F 12/1081 (2013.01); G06F 17/3061 (2013.01); G06F 17/30424 (2013.01); G06F 21/55 (2013.01); H04L 63/0227 (2013.01); H04L 67/10 (2013.01); Y02B 60/1225 (2013.01); Y02B 60/1228 (2013.01); Y02B 60/142 (2013.01); Y02B 60/167 (2013.01);
Abstract
A packet handling system is disclosed that can include at least one main processor; a plurality of offload processors connected to a memory bus and configured to provide security related services on packets prior to redirection to the main processor; and a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, the virtual switch configured to receive memory read/write data over the memory bus.