The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2017

Filed:

Apr. 07, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Christian Habermann, Boeblingen, DE;

Christian Jacobi, Poughkeepsie, NY (US);

Martin Recktenwald, Schonaich, DE;

Hans-Werner Tast, Weil im Schoenbuch, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/00 (2006.01); G06F 9/46 (2006.01); G06F 12/0811 (2016.01); G06F 12/0846 (2016.01); G06F 12/0897 (2016.01); G06F 12/0817 (2016.01); G06F 12/0875 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0811 (2013.01); G06F 12/0824 (2013.01); G06F 12/0846 (2013.01); G06F 12/0848 (2013.01); G06F 12/0875 (2013.01); G06F 12/0897 (2013.01); G06F 2212/283 (2013.01); G06F 2212/452 (2013.01); G06F 2212/622 (2013.01);
Abstract

A hierarchical cache structure comprises at least one higher level cache comprising a unified cache array for data and instructions and at least two lower level caches, each split in an instruction cache and a data cache. An instruction cache and a data cache of a split second level cache are connected to a third level cache; and an instruction cache of a split first level cache is connected to the instruction cache of the split second level cache, and a data cache of the split first level cache is connected to the instruction cache and the data cache of the split second level cache.


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