The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2017

Filed:

Apr. 10, 2015
Applicant:

Samsung Display Co., Ltd., Yongin, KR;

Inventors:

SeungBo Shim, Asan-si, KR;

Jeong Won Kim, Seoul, KR;

Kwangwoo Park, Hwaseong-si, KR;

Jinho Ju, Seoul, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); G02F 1/1362 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
G02F 1/136209 (2013.01); H01L 27/124 (2013.01); H01L 27/1288 (2013.01); H01L 29/66765 (2013.01); H01L 29/78669 (2013.01); G02F 1/136227 (2013.01); G02F 2001/136222 (2013.01); G02F 2001/136231 (2013.01); G02F 2001/136295 (2013.01);
Abstract

A method of manufacturing a display device, the method including: forming, on a first surface of a substrate, a gate line and a gate electrode; forming a first dielectric layer on the gate line and the gate electrode; forming a data line, a source electrode and a drain electrode on the first dielectric layer; forming a black matrix layer on the first dielectric layer, the data line, the source electrode, and the drain electrode; radiating ultraviolet light on a second surface of the substrate opposing the first surface, the ultraviolet light developing exposed parts of the black matrix layer to form a black matrix pattern; and etching the first dielectric layer using the black matrix pattern as an etching mask to respectively form a first dielectric pattern on the gate line and a gate dielectric pattern on the gate electrode.


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