The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 30, 2017
Filed:
Feb. 17, 2016
Globalfoundries Inc., Grand Cayman, KY;
Bichoy Bahr, Cambridge, MA (US);
Zoran Krivokapic, Santa Clara, CA (US);
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Abstract
A semiconductor structure includes a semiconductor substrate, fins coupled to the semiconductor substrate, FinFETs on the fins, a common gate for the FinFETs, a dielectric layer on the semiconductor substrate, the dielectric layer surrounding a cavity with the semiconductor substrate providing bottom confinement of the acoustic cavity by total internal reflection, and an interconnect structure above the FinFETs, the interconnect structure including phononic crystal(s) to confine acoustic energy in the cavity including the cavity and metal layer(s) sandwiched between two dielectric layers. The semiconductor structure may be realized, during FEOL fabrication of a FinFET, by forming a cavity on a surface of a semiconductor substrate. Then, after fabrication of the FinFET, forming an interconnect structure for the FinFET. During formation of the interconnect structure, materials of the interconnect structure are used to form a phononic crystal to confine the cavity between the phononic crystal and the semiconductor substrate.