The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2017

Filed:

Aug. 19, 2014
Applicant:

Sanmina Corporation, San Jose, CA (US);

Inventors:

Douglas Ward Thomas, Pacific Grove, CA (US);

Shinichi Iketani, Sunnyvale, CA (US);

Assignee:

SANMINA CORPORATION, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/10 (2006.01); H05K 3/42 (2006.01); H05K 3/00 (2006.01);
U.S. Cl.
CPC ...
H05K 3/427 (2013.01); H05K 3/0026 (2013.01); H05K 3/0047 (2013.01); H05K 2201/09845 (2013.01); H05K 2203/0207 (2013.01); Y10T 29/49165 (2015.01);
Abstract

Cost effective and efficient methods to maximize printed circuit board (PCB) utilization with minimized signal degradation are provided. The methods include electrically isolating a segmented via structure by controlling the formation of a conductive material within a plated via structure by utilizing different diameter drills within a via structure for trimming the conductive material at the via shoulder (i.e., the rim of a drilled two diameter hole boundary). The trimmed portion may be voided in the via structure for allowing electrically isolated plated through-hole (PTH) segments. One or more areas of trimmed rims within the via structure are used to form multiple stair like diameter holes to create one or more voids in the via structure. As a result, the formation of conductive material within the via structure may be limited to those areas necessary for the transmission of electrical signals.


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