The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2017

Filed:

Mar. 24, 2011
Applicants:

Stefan Weisser, Nuremberg, DE;

Silvio Cucchi, Gaggiano, IT;

Carlo Costantini, Casatenovo, IT;

Noriaki Kaneda, Westfield, NJ (US);

Andreas Leven, Bietigheim-Bissingen, DE;

Inventors:

Stefan Weisser, Nuremberg, DE;

Silvio Cucchi, Gaggiano, IT;

Carlo Costantini, Casatenovo, IT;

Noriaki Kaneda, Westfield, NJ (US);

Andreas Leven, Bietigheim-Bissingen, DE;

Assignee:

Alcatel Lucent, Boulogne-Billancourt, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 10/61 (2013.01); H03G 3/30 (2006.01); H04B 10/60 (2013.01); H04B 10/69 (2013.01); H04L 27/20 (2006.01); H04L 27/38 (2006.01);
U.S. Cl.
CPC ...
H04B 10/616 (2013.01); H03G 3/3084 (2013.01); H04B 10/60 (2013.01); H04B 10/613 (2013.01); H04B 10/6931 (2013.01); H04L 27/2096 (2013.01); H04L 27/3809 (2013.01); H04L 27/3818 (2013.01);
Abstract

It is disclosed an optical coherent receiver for an optical communication network. The optical coherent receiver is configured to receive a modulated optical signal and to process it for generating an in-phase component and a quadrature component. The optical coherent receiver comprises a power adjuster in turn comprising a multiplying unit and a retroactively connected digital circuit. The multiplying unit is configured to multiply the in-phase and quadrature components by in-phase and quadrature gains, respectively, thereby providing power-adjusted in-phase and quadrature components. The digital circuit is configured to compute: a common gain indicative of a sum of the powers of the power-adjusted in-phase and quadrature components; a differential gain indicative of a difference between the powers of the power-adjusted in-phase and quadrature components; and the in-phase and quadrature gains as a product and a ratio, respectively, between the common gain and the differential gain.


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