The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2017

Filed:

Apr. 15, 2015
Applicant:

Sandisk Technologies Inc., Plano, TX (US);

Inventors:

Ramakrishnan Karungulam Subramanian, Bangalore, IN;

Anand Venkitachalam, Bangalore, IN;

Jayaprakash Naradasi, Bangalore, IN;

Prashant Singhal, Bangalore, IN;

Assignee:

SanDisk Technologies LLC, Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/091 (2006.01); H03L 7/081 (2006.01); G06F 1/08 (2006.01); G06F 1/10 (2006.01); G06F 13/42 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
H03L 7/091 (2013.01); G06F 1/08 (2013.01); G06F 1/10 (2013.01); G06F 13/1689 (2013.01); G06F 13/4221 (2013.01); H03L 7/0812 (2013.01);
Abstract

Methods and circuits for delay compensation are provided. A data clock may be generated from a peripheral clock. Sample data may be provided in a data signal on a bus in response to an edge of the data clock, where the edge of the data clock is triggered by an initial edge of the peripheral clock. A delay of the data clock relative to the peripheral clock may be selected based on a time difference between the initial edge of the peripheral clock and a time at which the sample data is detected on the bus. A delayed data clock having the selected delay relative to the peripheral clock may be generated. Requested data may be provided on the bus in response to an edge of the delayed data clock.


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