The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2017

Filed:

Jul. 24, 2015
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventor:

Jun Cai, Allen, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/08 (2006.01); H01L 21/265 (2006.01); H01L 29/66 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7823 (2013.01); H01L 21/26513 (2013.01); H01L 27/0922 (2013.01); H01L 29/0634 (2013.01); H01L 29/0649 (2013.01); H01L 29/0653 (2013.01); H01L 29/0856 (2013.01); H01L 29/0873 (2013.01); H01L 29/1095 (2013.01); H01L 29/66681 (2013.01); H01L 29/78 (2013.01); H01L 21/823814 (2013.01);
Abstract

LDMOS devices are disclosed. An LDMOS device includes at least one drift region disposed in a portion of a semiconductor substrate; at least one isolation structure at a surface of the semiconductor substrate; a D-well region positioned adjacent a portion of the at least one drift region, and an intersection of the drift region and the D-well region forming a junction between first and second conductivity types; a gate structure disposed over the semiconductor substrate; a source contact region disposed on the surface of the D-well region; a drain contact region disposed adjacent the isolation structure; and a double buffer region comprising a first buried layer lying beneath the D-well region and the drift region and doped to the second conductivity type and a second high voltage deep diffusion layer lying beneath the first buried layer and doped to the first conductivity type. Methods are disclosed.


Find Patent Forward Citations

Loading…