The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2017

Filed:

Mar. 25, 2015
Applicant:

SK Hynix Inc., Icheon-si, Gyeonggi-do, KR;

Inventors:

Kyu Bong Kong, Suwon-si, KR;

Kwang Jin Na, Seoul, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); H01L 25/065 (2006.01); G11C 8/18 (2006.01); G11C 29/02 (2006.01); G11C 7/10 (2006.01); H01L 25/18 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0655 (2013.01); G11C 7/1066 (2013.01); G11C 7/1093 (2013.01); G11C 8/18 (2013.01); G11C 29/023 (2013.01); G11C 29/028 (2013.01); G11C 2207/2254 (2013.01); H01L 25/18 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A semiconductor package may include a first die, a second die disposed adjacent to the first die, and configured to share an address with the first die. The semiconductor package may include a first address pin included with the first die, and configured for receiving the address. The semiconductor package may include a second address pin included with the second die, and configured for receiving the address. The first die and the second die may output data corresponding to the address. Timings of the address in the first die and the second die may be aligned according to delay signals applied from a controller.


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