Circuit for reading one time programmable memory

Abstract

A circuit for reading a one time programmable (OTP) memory includes a controller that receives a read input signal and generates a read delay signal, a read voltage signal, and a read latch signal; a read voltage generator that generates a read voltage based on the read voltage signal and outputs the read voltage to a detecting node; an OTP memory unit cell including a first electrode connected to the detecting node; a first detecting unit that determines a voltage at the detecting node; a determining unit that delays an output signal from the first detecting unit based on the read delay signal; and a latch unit that latches an output signal from the determining unit during a first delay time at a falling edge of the read input signal based on the read latch signal.