The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2017

Filed:

Feb. 17, 2015
Applicants:

Technion Research and Development Foundation Ltd., Haifa, IL;

University of Rochester;

Inventors:

Avinoam Kolodny, Haifa, IL;

Shahar Kvatinsky, Ramat Gan, IL;

Ravi Patel, Victor, NY (US);

Eby Friedman, Rochester, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01); G06F 9/30 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0069 (2013.01); G06F 9/30101 (2013.01); G11C 13/0004 (2013.01); G11C 13/004 (2013.01); G11C 13/0007 (2013.01); H01L 27/24 (2013.01);
Abstract

A multistate register, comprising: a flip-flop that comprises a first latch, a second latch and an intermediate gate coupled between the first and second latches; multiple memristive devices; and an interface coupled between the multiple memristive devices and the flip-flop; wherein the multistate register is arranged to operate in a memristive device write mode, in a memristive device read mode and in a flip-flop mode; wherein when operating in the memristive device read mode, the interface is arranged to write to a first selected memristive device of the multiple memristive devices a first logic value stored in the first latch; wherein when operating in the memristive device write mode, the interface is arranged to write to the second latch a second logic value stored in a second selected memristive device of the multiple memristive devices; and wherein when operating on a flip-flop mode logic the interface is prevented from transferring values between the flip flop and the memristive devices.


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